CURPIPE=Others, BIGEND=0, REW=0, RCNT=0, MBW=00, ISEL=0
CFIFO Port Selection Register
| CURPIPE | FIFO Port Access Pipe Specification 0 (0x0): DCP (default control pipe) 0 (Others): Setting prohibited 1 (0x1): Pipe 1 2 (0x2): Pipe 2 3 (0x3): Pipe 3 4 (0x4): Pipe 4 5 (0x5): Pipe 5 6 (0x6): Pipe 6 7 (0x7): Pipe 7 8 (0x8): Pipe 8 9 (0x9): Pipe 9 |
| ISEL | FIFO Port Access Direction when DCP Is Selected 0 (0): Select reading from the FIFO buffer 1 (1): Select writing to the FIFO buffer |
| BIGEND | FIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| MBW | CFIFO Port Access Bit Width 0 (00): 8-bit width 1 (01): 16-bit width 2 (10): 32-bit width 3 (11): Setting prohibited |
| REW | Buffer Pointer Rewind 0 (0): Do not rewind buffer pointer (Writing 0 has no effect.) 1 (1): Rewind buffer pointer |
| RCNT | Read Count Mode 0 (0): Clear DTLN[11:0] flags in the FIFO port control register to 0x000 when all receive data is read from CFIFO 1 (1): Decrement DTLN[11:0] flags each time receive data is read from CFIFO |